1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, relates to a semiconductor device having transmission transistors co-operating in pairs.
2. Description of Related Art
Recent years have seen advances in miniaturization of the fabrication process of a semiconductor device. This miniaturization generates a problem in that even the same-sized transistors provide a variation of drive capability depending on the element shape. If a plurality of transistors co-operating in pairs (hereinafter referred to as pair operation) provide a variation of drive capability, then the pair capability is reduced, thereby causing a problem in that circuit operation may fail. As an example of a transistor performing pair operation, there has been known a dual port static random access memory cell (hereinafter referred to as a dual port SRAM cell). An example of this dual port SRAM cell is disclosed in Patent Document 1.
FIG. 10 shows a circuit diagram of the dual port SRAM cell 100 disclosed in Japanese Patent Laid-Open Application No. 2002-222874. As shown in FIG. 10, the dual port SRAM cell 100 has a first bit line pair (Bit A and Bit A/) connected to a first port and a second bit line pair (Bit B and Bit B/) connected to a second port. On the one hand, data input/output between the first bit line pair and the memory cell storage nodes ND and ND/ is performed via transmission transistors 110 and 111. On the other hand, data input/output between the second bit line pair and the memory cell storage nodes ND and ND/ is performed via transmission transistors 120 and 121.
FIG. 11 shows a schematic view of a plane layout of the dual port SRAM cell 100. As shown in FIG. 11, the dual port SRAM cell 100 has a first region 102, on which load transistors (140 and 141) composed of PMOS transistors are formed; and a second region 101a and a third region 101b, on which drive transistors (130 and 131) and transmission transistors (110, 111, 120, and 121) composed of NMOS transistors are formed. The dual port SRAM cell 100 arranges the second region 101a and the third region 101b by sandwiching the first region 102 therebetween. This arrangement of the second region 101a and the third region 101b allows the first bit line pair and the second bit line pair to be arranged via a power line supplying power to load transistors 140 and 141. The dual port SRAM cell 100 provides this layout to prevent a signal interference generated between the first bit line pair and the second bit line pair.
Here, the dual port SRAM cell 100 provides pair operation of the transmission transistors 110 and 111 connected to the first bit line pair and provides pair operation of the transmission transistors 120 and 121 connected to the second bit line pair. In the dual port SRAM cell 100, the transmission transistors performing pair operation are connected to different storage nodes. For that reason, the transmission transistors performing pair operation must be same in transistor size, but must be isolated with each other. The dual port SRAM cell 100 provides the same gate length and the same gate width of the transmission transistors performing pair operation to equalize the transistor sizes; and provides an element isolation region STI to isolate the two transistors.
Unfortunately, in the dual port SRAM cell 100, the transmission transistor 110 and the transmission transistor 111 are different in shape of diffused region. With reference to FIG. 11, the diffused region at the side of the storage node ND/ of the transmission transistor 111 is integrally formed with the diffused region of the drive transistor 131; and an element isolation region STI (region C in the figure) is formed between the diffused region at the side of the storage node ND of the transmission transistor 110 and the diffused region of the drive transistor 131 and the diffused region of the transmission transistor 111.
In general, in an element isolation region STI (Shallow Trench Insulation), a mechanical stress on silicon changes depending on the STI forming conditions such as an embedding temperature and a film quality. When a compression stress is added to an NMOS transistor in a channel direction, the mobility is lowered. For that reason, in the case of the layout shown in FIG. 11, the transmission transistor 110 receives a large stress from the element isolation region STI (hereinafter referred to as an STI stress) positioned in region C, and the transmission transistor 111 has a small effect of the STI stress from the element isolation region STI. When a transistor receives an STI stress, the STI stress causes a strain of the silicon crystal, and the strain causes a variation of the drive capability. In other words, the layout of the dual port SRAM cell 100 disclosed in the above mentioned Japanese Patent Publication has a problem in that the transmission transistors performing pair operation causes a variation of drive capability due to the STI stress. FIG. 12 shows a graph showing the drive capability for the individual bit line pairs of the dual port SRAM cell 100. As shown in FIG. 12, for the dual port SRAM cell 100, the drive capabilities for the bit line Bit A and the bit line Bit B/ are low (for example, about −5% with respect to the average value) and the drive capabilities for the bit line Bit A/ and the bit line Bit B are high (about +5% with respect to the average value).